CPU cache simulator

Choose a cache configuration and an access pattern, or enter a custom trace, then select Run. Presets are illustrative configurations, not measurements of a particular processor. Changing an input or source tab cancels the current calculation and clears both results. Clear results retains the inputs.

The model starts with one empty cache. Each access reads or writes an aligned 4-byte word at a 32-bit byte address from 0 to 4294967292. Capacity is 1–2048 KiB; line size is 8–256 B. Associativity cannot exceed the number of lines. Mapping uses block = floor(address / line size) and set = block modulo set count.

Write-back with write-allocate: a miss fetches one line; a store marks it dirty. A dirty eviction writes the whole line. Dirty lines remaining at the end are reported separately and are not automatically flushed. Write-through without write-allocate: each store writes 4 B; a store miss does not fill a cache line. Read and write traffic describe this trace model, not hardware performance counters.

Miss causes: for LRU with write-back/write-allocate, first contact with a block is compulsory. Later misses are capacity misses if an equal-capacity fully associative LRU cache also misses, otherwise conflict misses. FIFO, Random and write-through/no-allocate report first-contact and further misses only; this does not separate policy, mapping and capacity effects. LRU replaces the least recently used line; FIFO replaces the earliest inserted line. Random choices use fixed seeds and are reproducible, not cryptographic. Modulo mapping can introduce a small bias for working sets whose size is not a power of two.

Traces: put one access on each line, for example R 0x0, W 4 or 1024 (read by default). Blank lines and whole lines beginning with # are ignored. Invalid lines are rejected; nothing is silently skipped or truncated. Limits are 1200000 accesses and 48 Mi characters of input text. Only the first 64 steps appear in the table; totals cover the full trace.

Generated arrays contain 4-byte elements. Matrices are row-major, with A, B and C placed consecutively. The multiplication traces read and write C for each tile; transposition reads A and writes B. Matrix N is 2–64 for multiplication and 2–512 for transposition; a tile is 1–N. Stride is a multiple of 4 and must keep every address within the 32-bit range. Random accesses use the chosen working set.

Costs and comparison: AMAT = hit cost + miss rate × miss surcharge. Both costs may be 0–10⁹ cycles. This constant-cost model does not simulate write buffers, overlapping accesses or multiple cache levels. The capacity comparison uses the same first at most 150000 accesses for every configuration and reports their miss rates, not a guaranteed steady-state rate.

Inputs, including unfinished or invalid drafts, are saved locally up to 100000 serialized characters. Above this limit, the previous saved copy is retained and a warning appears: download the full trace before reloading or leaving the page. Navigation within this app keeps the live session and completed result. A full reload restores the saved inputs and waits for Run. Traces omitted by older versions cannot be recovered.

Sources: Cornell CS3410: Caches and Dinero IV: trace-driven cache simulation.

The overview and set chart show the complete simulation. Expand Access steps for the individual records; a sample-limit note appears only when the trace is longer than the displayed table. Numeric columns align with their headers and wide tables scroll locally. Costs and capacity comparison remain optional.

The chart uses set indices horizontally and access counts vertically. Blue bars show all accesses; red bars overlay their misses, not additional accesses. Adjacent sets are grouped when space is limited; each column sums their counts.