AVX2 Simulator

Build a pipeline of up to eight AVX2 or listed AVX floating-point intrinsics, then press Run. Input edits clear every result; nothing executes automatically. Reset results preserves your inputs. Changing the output view only reinterprets the existing result bits and remains selected on the next run. Reopening the tool starts with the inactive addition example; long pipelines and memory are not saved. Copy values exports the selected vector interpretation, the unsigned scalar mask, or all 256 memory bytes after a store.

Each operand has its own explicit view. Lane 0 is the low-bit lane and is entered first, reading left to right. Integer input is signed or unsigned base-10 within the chosen type’s range; 64-bit integers remain exact. Numbers are separated by commas or whitespace, without empty comma entries. Float input uses a decimal point and may use an exponent, NaN, Infinity, -Infinity or -0. A finite value that overflows the chosen float type is rejected. Hex input uses complete byte pairs; bit input uses the highest bit first within each byte. Bytes themselves always run from low to high address. Enter the exact number of values shown; no padding, truncation or paste-based type detection occurs.

The intrinsic determines arithmetic, lane width and signedness; choosing u32 instead of i32 changes the view of the bits, not the instruction. Changing an input view reformats valid existing bits; invalid draft text is retained for correction. Output tables show lane indices, bit ranges, the selected view, integer counterparts where applicable, and little-endian bytes. Separate table sections identify the 128-bit halves. Flags identify saturation, wraparound, operations within halves and special source or mask rules.

Use previous result connects only a vector of exactly the required width to the first operand. Its text is filled after a successful run. A scalar movemask or a store’s memory result cannot be chained as a vector. No implicit widening from 128 to 256 bits occurs. Uncheck the option to use a manual operand. Scalar masks are displayed separately as unsigned decimal and hexadecimal values.

Memory operations share a 256-byte source entered as hex. A run works on a copy: stores feed later memory operations in that run but do not overwrite the source text. Base offsets and gather scales are byte-based; gather indices are signed. Bounds apply only to active accesses. An inactive masked lane has no evaluated address and is shown with a dash. The high mask bit determines selection. Stream loads require 32-byte alignment; loadu accepts unaligned addresses. Stores show changed bytes and optional complete memory; access details also show writes that leave a byte unchanged.

Examples cover addition, integer wraparound, saturation, byte shuffling within 128-bit halves, an unaligned load at offset 3, and add followed by shift. The shuffle example uses a high control bit to zero its first byte. Each example only prepares inputs; Run performs the calculation. If any step fails, the pipeline publishes no partial result.

This is a learning simulation, not a CPU emulator. It does not model timing, CPU flags, MXCSR modes, NaN payloads, caches or hardware faults. Float operations use normal IEEE f32/f64 values with JavaScript round-to-nearest behavior; results may be Infinity or NaN. Source: Intel Intrinsics Guide.