Wireworld

All cells update simultaneously from the old field. Empty stays empty, an electron head becomes a tail, and a tail becomes conductor. Conductor becomes a head only with exactly one or two head neighbours among its eight Moore neighbours; the centre is excluded. The fixed 32 × 20 field either has an empty outside or wraps opposite edges. It fits its container without changing cell proportions.

The AND preset starts both inputs at generation 0. Checked means an initial head, unchecked means conductor; no initial tail is needed at these endpoints. A is at column 9, row 6; B at column 5, row 8; Q at column 27, row 13. Q is sampled at generation 22: only A=B=1 produces a head there. Expected Q is Boolean AND; observed Q comes from the simulated cell, with 1 meaning a head and 0 its absence. The straight wire has one initial pulse and samples its endpoint at generation 21.

Observe output advances only the remaining generations up to the sample. Run pauses when that generation is reached; Step also pauses before one exact generation. Later steps retain the labelled sample rather than presenting it as the current Q state. Circuit, input or boundary changes wait for Load. Rate changes pause while preserving progress.

View keeps touch and wheel scrolling. In Paint mode, choose any of the four states and draw; a whole stroke commits on release, while cancellation leaves the field unchanged. Arrow keys move the cursor; Space/Enter paints and Delete clears. The cursor reports its current state, neighbouring head count and next state. Any effective edit starts a custom circuit at generation 0 and removes the reference interpretation. Reset restores the latest loaded or edited starting field and its input settings, paused. There is no undo history.

Playback processes at most four generations per frame and reports discarded waiting time without skipping logical generations. Hiding the tool or browser tab pauses it. Saved state includes the current field, starting field, progress, sampled output and controls; reload remains paused. Both fields are packed within the existing bounded state mechanism. A warning appears if the encoded state exceeds the storage limit.

Rules: Wireworld rules. Timing: Signals and timing. AND layout adapted from Harold V. McIntosh’s first circuit in Golly gate-AND.mcl, translated and shortened by one terminal conductor cell. This is a discrete signal experiment, not an electrical circuit simulator.