Simulador de caché de CPU

Runs an address trace through a configurable set-associative cache and reports what a hardware performance counter would tell you: hit rate, where the misses come from, how many bytes crossed the memory bus, and the average memory access time.

Configuration

• Cache size and line size — capacity, and how many bytes are fetched per miss. A larger line exploits spatial locality but wastes bandwidth on random access.
• Associativity — lines per set. 1-way is direct-mapped (one possible home per address, cheap but conflict-prone), fully associative has a single set (no conflicts, expensive hardware).
• Replacement — LRU evicts the least recently used line, FIFO the oldest, Random picks a victim at random. Real caches use approximations of LRU.
• Write policy — write-back with write-allocate fetches the line on a store and writes it out only when a dirty line is evicted; write-through, no write-allocate sends every store (4 bytes here) straight to memory and does not allocate on a store miss.
• Hit time and miss penalty feed the AMAT formula below.

Address split: with a 32-bit address, the low log2(line size) bits are the block offset, the next log2(number of sets) bits select the set, and the rest is the tag stored alongside each line.

Traces. The generator produces the classic access patterns: a sequential scan, a strided scan (try a stride equal to the line size, then to the cache size divided by the associativity), naive and tiled matrix multiply, a matrix transpose, and uniform random access. You can also paste your own trace: one access per line as R 0x1000 or W 4096; a bare address counts as a read, and # starts a comment.

The three Cs. Every miss is one of: compulsory (the line had never been touched — unavoidable without prefetching), capacity (it would also have missed in a fully associative cache of the same size — the working set is too big), or conflict (a fully associative cache would have hit — too many hot lines mapped to the same set). Conflict misses are the ones you can fix by padding arrays, changing the layout or raising associativity.

AMAT = hit time + miss rate × miss penalty, in cycles. It is the number that decides whether a cache change is worth it.

Accesses per set shows the access count per set in blue with the misses in red. A few tall red spikes mean conflict misses concentrated in a handful of sets, the classic symptom of a power-of-two array stride.

Example — why blocking works: pick the textbook 8 KB direct-mapped preset and the naive matrix multiply with N = 64. The miss rate is about 51% and AMAT sits near 45 cycles, with roughly 88% of the misses classified as conflict. Switch to the tiled version with a tile of 8 and the miss rate drops to about 5% and AMAT to 8 cycles, for exactly the same arithmetic — the tile keeps the working set inside the cache.

Example — conflict misses: run the transpose with N = 128 on the 32 KB 8-way cache. Over 85% of the misses are conflicts, because the column walk strides by a power of two and lands in the same handful of sets. Raising the line size or padding the row length would spread them out.

Limitations: a single level of cache, no prefetcher, no TLB, no sub-block or critical-word-first effects, and stores are treated as 4 bytes for write-through traffic. Traces are capped at 1.2 million accesses.